Integrated circuit design and implementation is becoming more and more complex as the functionality and size of the circuits increases. A variety of users and manufacturers of devices utilizing integrated circuits desire an increasing array of functionality and performance in lower cost devices. To provide this functionality, producers of integrated circuits must become more efficient in the design and optimization of the circuits to ensure competitive positioning of their products.
One such area for optimization includes the use of “flows”. Flows include procedures for taking semiconductor devices from concept to physical realization by invoking a succession of software design tools which implement logical and physical operations necessary for optimizing and verifying the correct behavior of the device. However, as the complexity of the integrated circuit increases, so does the complexity of the design flow.
For example, high complexity semiconductor devices, such as system-on-chip devices and the like, may be organized as networks or interconnected patterns of functional blocks which include a variety of semiconductor functional elements. However, changes to the functional blocks, changes to the elements of the functional blocks, routing between blocks and elements, and the like at one stage of the flow may affect earlier flow stages. Therefore, the resultant product may have inconsistencies and incompatibilities that must be addressed before a working product is realized.
Therefore, it would be desirable to provide a system and method for an interactive representation of structural dependencies in semiconductor design flows.